1. Field of the Disclosure
This disclosure generally relates to a liquid crystal display and, more particularly, to an integrated gate driver circuit and a liquid crystal panel using the same.
2. Description of the Related Art
The conventional liquid crystal display generally includes a plurality of gate driver circuits configured to drive a pixel matrix. In order to reduce the manufacturing cost and to efficiently use the substrate space, gate drivers and the pixel matrix can both be formed on the substrate surface, wherein said gate drivers are named the integrated gate driver circuit.
Referring to FIG. 1, it shows a schematic block diagram of the conventional integrated gate driver circuit 9 including a control circuit 91 and a plurality of drive stages 921-924 . . . . The control circuit 91 outputs a plurality of clock signals CLK to the drive stages 921-924 . . . , and the clock signals CLK include, for example, CLK1-CLK4, refer to FIG. 2. The drive stages 921-924 . . . respectively output an output signal Output 1-Output 4 . . . for driving one gate line.
Referring to FIG. 2, it shows a timing diagram of the clock signals and the output signals of the integrated gate driver circuit 9 shown in FIG. 1. Firstly the control circuit 91 outputs a start vertical frame signal STV to the first drive stage 921 and then sequentially outputs a part of the clock signals CLK1-CLK4 (e.g. CLK1-CLK3) to every drive stage. After receiving a part of the clock signals CLK, the first drive stage 921 outputs an output signal Output 1, which is a replica of the first waveform of the clock signal CLK1; after receiving a part of the clock signals CLK the second drive stage 922 outputs an output signal Output 2, which is a replica of the first waveform of the clock signal CLK2; after receiving a part of the clock signals CLK the fifth drive stage 925 outputs an output signal Output 3, which is a replica of the second waveform of the clock signal CLK1; after receiving a part of the clock signals CLK the sixth drive stage 926 outputs an output signal Output 4, which is a replica of the second waveform of the clock signal CLK2; and so on.
In order to reduce the power consumption of the integrated gate driver circuit 9, the control circuit 91 will stop outputting any clock signal to the drive stages 921-924 . . . between two image frames; that is, in a time interval after the last drive stage outputs an output signal Output n of a first image frame and before the first drive stage 921 outputs an output signal Output 1 of a second image frame, referring to FIG. 3, the control circuit 91 does not output any clock signal. However, during the time interval that the drive stages 921-924 . . . do not receive any clock signal, the voltage value of the output signals Output 1-Output n . . . may have the voltage fluctuation as shown in FIG. 3, and this voltage fluctuation can influence the gate driving signals in the second image frame.
Accordingly, the present disclosure further provides an integrated gate driver circuit and a liquid crystal panel that can eliminate the voltage fluctuation on the gate lines in a blanking period between two image frames.